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a6282 description the a6282 device is designed for led display applications. this cmos device includes an input shift register, accompanying data latches, and 16 mos constant current sink drivers. the cmos shift registers and latches allow direct interfacing with microprocessor-based systems. with a 3.3 or 5 v logic supply, typical serial data input rates can reach up to 30 mhz. the led drive current level can be set by a single external resistor, selected by the application designer. a serial data output permits cascading of multiple devices in applications requiring additional drive lines. the a6282 is available in two 24-terminal packages: qfn (package es) and tssop (lp), which have an exposed thermal pad. both packages are lead (pb) free with 100% matte tin leadframe plating. applications include the following: ? monocolor, multicolor, or full-color led display ? monocolor, multicolor, or full-color led signboard ? display backlighting ? multicolor led lighting 6282-ds, rev. 4 features and benefits ? 16 constant-current outputs, up to 50 ma each ? led output voltage up to 12 v ? 3.0 to 5.5 v logic supply range ? schmitt trigger inputs for improved noise immunity ? power-on reset (por), all register bits = 0 ? low-power cmos logic and latches ? high data input rate: 30 mhz ? output current accuracy: between channels < 3% and between ics 7%, over the full operating temperature range ? internal uvlo and thermal shutdown (tsd) circuitry 16-channel constant-current led driver typical application controller clk le sdo rext a6282 ic 1 a6282 ic 2 oe sdi sdi 10 f 100 nf out0 out15 v led v dd clk le oe clk le oe rext 100 nf v dd 10 f out0 out15 sdo sdi gnd gnd vdd vdd not to scale 24-contact qfn 4 mm 4 mm 0.75 mm (package es) 24-pin tssop with exposed thermal pad (package lp) cascaded a6282 devices packages:
16-channel constant-current led driver a6282 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit supply voltage* v dd ?0.3 to 5.5 v outx current (any single output) i o 60 ma input voltage range* v i v oe , v le , v clk , v sdi ?0.3 to v dd + 0.3 v led load supply range* v led ?0.3 to 13.2 v esd rating hbm (jedec jesd22-a114, human body model) 2.0 kv cdm (jedec jesd22-c101, charged device model) 1.0 kv operating temperature range (e) t a ?40 to 85 c junction temperature t j (max) 150 c storage temperature range t stg ?55 to 150 c *with respect to ground. selection guide part number package packing a6282eestr-t 4 mm 4 mm qfn, 24 pins, exposed thermal pad 1500 pieces per 7-in. reel a6282elptr-t tssop, 24 pins, exposed thermal pad 4000 pieces per 13 in. reel thermal characteristics characteristic symbol test conditions 1 value units package thermal resistance r ja es package, 4-layer pcb based on jedec standard 37 c/w lp packge, 4-layer pcb based on jedec standard 28 c/w *additional thermal information available on the allegro website. 50 75 100 125 150 25 allowable package power dissipation (w) ambient temperature (c) 5.0 0 1.0 2.0 3.0 4.0 package lp, r q ja = 28 c/w package es, r q ja = 37 c/w
16-channel constant-current led driver a6282 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram inputs and outputs equivalent circuits resistor values are equivalent resistance and not tested vdd clk, sdi, le, o e 500 sdo vdd 10 sdo sdi le out0 out1 out15 uvlo and tsd vdd i o regulator rext serial - parallel shift register control logic block clk output control drivers v led exposed pad (et and lp packages) oe gnd la t ches
16-channel constant-current led driver a6282 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table name number description es lp clk 6 3 clock; data shift clock input terminal gnd 4 1 logic supply ground and load supply ground le 7 4 latch enable input terminal o e 24 21 output enable input terminal, active low (when o e = high, all outx outputs are forced off; when o e = low, on/off status of outx outputs is controlled by the state of the latches out0 8 5 constant current outputs out1 9 6 out2 10 7 out3 11 8 out4 12 9 out5 13 10 out6 14 11 out7 15 12 out8 16 13 out9 17 14 out10 18 15 out11 19 16 out12 20 17 out13 21 18 out14 22 19 out15 23 20 pad ? ? exposed pad for enhanced thermal dissipation; not connected internally, connect to gnd rext 2 23 reference current terminal; sets output current for all channels sdi 5 2 serial data in terminal sdo 1 22 serial data out terminal vdd 3 24 logic supply terminal pin-out diagrams top-down views 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vdd rext sdo oe out15 out14 out13 out12 out11 out10 out9 out8 pad gnd sdi clk le out0 out1 out2 out3 out4 out5 out6 out7 pad 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 oe out15 out14 out13 out12 out11 le out0 out1 out2 out3 out4 out10 out9 out8 out7 out6 out5 sdo rext vdd gnd sdi clk es package lp package
16-channel constant-current led driver a6282 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a 1 = 25c, v dd = 3.0 to 5.5 v, unless otherwise noted characteristic symbol test conditions min. typ. 2 max. unit logic supply voltage range v dd operating 3.0 5.0 5.5 v led load supply output voltage v led operating ? ? 12.0 v undervoltage lockout v dd(uv) v dd 0 5.0 v 2.5 2.7 2.9 v v dd 5 0.0 v 2.3 2.5 2.7 v output current i o v dd = 4.5 to 5.5 v, v ds( x ) = 1 v, r ext = 374 ? 47.4 51.1 54.5 ma v dd = 3.0 to 3.6 v, v ds( x ) = 1 v, r ext = 374 ? 46.5 50.1 53.5 ma v dd = 4.5 to 5.5 v, v ds( x ) = 1 v, r ext = 910 ? 19.8 21.4 22.8 ma v dd = 3.0 to 3.6 v, v ds( x ) = 1 v, r ext = 910 ? 19.5 21.0 22.4 ma output current shift % ? i o v dd = 5.5 v, v ds( x ) = 1 v, r ext = 910 , t a = 25c; between one output on and all outputs on ? ? 1 % output to output matching error 3 err v ds = 1 v, r ext = 374 ? , all outputs on ? +1.0 +3.0 % v ds = 1 v, r ext = 910 ? , all outputs on ? +1.0 +3.0 % output current regulation %i o(reg) v dd = 5.5 v, v ds( x ) = 1 to 3 v, r ext = 374 ? , all outputs on ? 1.7 3 %/v v dd = 5.5 v, v ds( x ) = 1 to 3 v, r ext = 910 ? , all outputs on ? 2.4 4 %/v v dd = 3.6 v, v ds( x ) = 1 to 3 v, r ext = 374 ? , all outputs on ? 1.2 2 %/v v dd = 3.6 v, v ds( x ) = 1 to 3 v, r ext = 910 ? , all outputs on ? 1.8 3 %/v output leakage current i dss v oh = 12 v ? ? 0.5 a logic input voltage v ih 0.8v dd ?v dd v v il gnd ? 0.2v dd v logic input voltage hysteresis v ihys all digital inputs 250 ? 900 mv logic input current i i all digital inputs ?1 ? 1 a sdo voltage v ol i ol = 1 ma ? ? 0.5 v v oh i oh = ?1 ma v dd ? 0.5 ? ? v supply current 4 i dd(off) r ext = 3.8 k ? , v oe = 5 v ? ? 6 ma r ext = 910 ? , v oe = 5 v ? ? 16 ma r ext = 374 ? , v oe = 5 v ? ? 40 ma i dd(on) all outputs on, r ext = 910 ? , v o = 1 v, data transfer 30 mhz ? ? 20 ma all outputs on, r ext = 374 ? , v o = 1 v, data transfer 30 mhz ? ? 45 ma continued on the next page?
16-channel constant-current led driver a6282 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued), at t a 1 = 25c, v dd = 3.0 to 5.5 v, unless otherwise noted characteristic symbol test conditions min. typ. 2 max. unit switching characteristics at t a 1 = 25c, v dd = v ih = 5.0 v, v ds = 1 v, v il = 0 v, r ext = 910 , i o = 21.4 ma, v l = 2 v, r l = 51 , c l = 15 pf (see also timing diagrams section) characteristic symbol test conditions min. typ. 2 max. unit clock frequency f clk clk ? ? 30 mhz clock frequency (cascaded devices) f clkc clk ? ? 25 mhz clock pulse duration t wh0 clk = high 16 ? ? ns le pulse duration t wh1 le = high 20 ? ? ns setup time t su0 sdi to clk 10 ? ? ns t su1 clk to le 10 ? ? ns hold time t h0 clk to sdi 10 ? ? ns t h1 le to clk 10 ? ? ns rise time t r0 sdo, 10/90% points (measurement circuit a) ? ? 16 ns t r1 outx, v dd = 5 v,10/90% points (measurement circuit b) ? 10 30 ns fall time t f0 sdo, 10/90% points (measurement circuit a) ? ? 16 ns t f1 outx, v dd = 5 v,10/90% points (measurement circuit b) ? 10 30 ns propagation delay time t pd0 clk to sdo (measurement circuit a) ? ? 30 ns t pd1 o e to outx (measurement circuit b) ? ? 60 ns t pd2 le to outx (measurement circuit b) ? ? 60 ns output enable pulse duration t w(oe) (see timing diagrams section) 60 ? ? ns 1 tested at 25c. specifications are assured by design and characterization over the operating temperature range of ?40c to 85c . 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. thermal shutdown temperature t jtsd temperature increasing ? 165 ? c thermal shutdown hysteresis t jtsdhys ?15?c reference voltage at external resistor rext v ext r ext = 374 ? ? 1.21 ? v 1 tested at 25c. specifications are assured by design and characterization over the operating temperature range of ?40c to 85c . 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 3 err = (i o (min or max) ? i o (av)) / i o (av). i o (av) is the average current of all outputs. i o (min or max) is the output current with the greatest difference from i o (av). 4 recommended operating range: v o = 1.0 to 3.0 v. sdo 15 pf outx a6282 r l v l c l a6282 parameter measurement circuits (a) circuit for t f0 , t pd0 , and t r0 (b) circuit for t f1 , t pd1 , t pd2 , and t r1 .
16-channel constant-current led driver a6282 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com wh0 t su0 t h0 t pd0 t wh1 t su1 t clk sdi sdo le outx (current) pd2 t oe low = all outputs enabled high = output on low = output off outx (current) oe pd1 t pd1 t 50% 50% 50% r0 t f0 t 10% 90% f1 t r1 t 90% 10% 50% w (oe) t timing diagrams disabling outputs normal operation
16-channel constant-current led driver a6282 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics r ext = 470 r ext = 910 0 50 45 40 35 30 25 20 15 10 5 0 60 50 40 30 20 10 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 0.3 1.0 2.0 3.0 4.0 5.0 v ds (v) i o (max) (ma) i o (ma) r ext (k ) v dd (v) 4.5 to 5.0 3.0 to 3.6 channel maximum constant output current versus external reference resistance input-output truth table serial data input (sdi) clock input (clk) shift register contents serial data out (sdo) latch enable input (le) latch contents output enable input ( o e ) output contents i 0 i 1 i 2 ? i 15 i 0 i 1 i 2 ? i 15 i 0 i 1 i 2 ? i 15 h h r 0 r 1 ? r 15 r 14 l l r 0 r 1 ? r 15 r 14 x r 0 r 1 r 2 ? r 15 r 15 x x x ? x x l r 0 r 1 r 2 ? r 15 p 0 p 1 p 2 ? p 15 p 15 h p 0 p 1 p 2 ? p 15 l (outputs on) p 0 p 1 p 2 ? p 15 x x x ? x h (outputs off) h h h ? h l = low logic (voltage) level, h = high logic (voltage) level, x = don?t care, p = present state, r = previous state channel output current versus output voltage v dd = 5.0 v
16-channel constant-current led driver a6282 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com normal operation serial data present at the sdi (serial data in) input is transferred to the shift register on the transition from logic 0 to logic 1 of the clk (clock) input pulse. on succeeding clk pulses, the register shifts data towards the sdo (serial data out) output. the serial data must appear at the input prior to the rising edge of the clk waveform. data present in any register is transferred to the respective latch when the le (latch enable) input is high (serial-to-parallel con- version). the latches continue to accept new data as long as le is held high (level triggered). applications where the latches are bypassed (le tied high) require that the o e (output enable) input be high during serial data entry. when o e is high, the output sink drivers are disabled (off). the data stored in the latches is not affected by the state of o e . with o e active (low), the outputs are controlled by the state of their respective latches. setting maximum channel current the maximum output current per channel is set by a single exter- nal resistor, rext, which is placed between the rext pin and gnd. the voltage on rext, v ext , is set by an internal band gap and is 1.21 v, typical. the maximum channel output current can be calculated as: i o (max) = (18483.1/ r ext ) + 0.67 , for v dd = 3.0 to 3.6 v , or i o (max) = (18841.2/ r ext ) + 0.68 , for v dd = 4.5 to 5.5 v , where r ext is the value of the user-selected external resistor, which should not be less than 374 . a chart of the maximum per channel (out0 to out15) constant output current, i o (max), at various values of r ext , is shown in the operating characteristics section. undervoltage lockout the a6282 includes an internal undervoltage lockout (uvlo) circuit that disables the outputs in the event that the logic supply voltage drops below a minimum acceptable level. this feature prevents the display of erroneous information, a necessary func- tion for some critical applications. upon recovery of the logic supply voltage after a uvlo event, all internal shift registers and latches are set to 0. the a6282 is then in normal mode. thermal shutdown protection if the junction temperature exceeds the threshold temperature, t jtsd , 165c typical, the outputs will be turned off until the junc- tion temperature cools down through the thermal shutdown hys- teresis, 15c typical. the shift register and output latches register will remain active during a thermal shutdown event. therefore, there is no need to reset the data in the output latches. functional description
16-channel constant-current led driver a6282 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com load supply voltage (v led ) this device is designed to operate with driver voltage drops (v ds ) of 1.0 to 3.0v. if higher voltages are dropped across the driver, package power dissipation will increase. to minimize package power dissipation, it is recommended to use the lowest possible load supply voltage, v led , or to set a series voltage drop, v drop , according to the following formula: v drop = v led ? v f ? v ds , where v f is the led forward voltage. for reference, typical led forward voltages are: led type v f (v) white 3.5 to 4.0 blue 3.0 to 5.5 green 1.8 to 2.5 yellow 2.0 to 2.5 amber 1.9 to 3.0 red 1.6 to 2.5 infrared 1.2 to 1.8 uv 3.0 to 4.0 v drop = i o r drop for a single driver, for a zener diode (v z ), or for a series string of silicon diodes (approximately 0.7 v per diode) for a group of drivers (these configurations are shown in the figure below). if the available voltage source will cause unacceptable power dissipation and series resistors or diodes are undesirable, a voltage regulator can be used to provide v led . pattern layout to save pins and board space, the a6282 uses one pin for both logic ground and power ground. therefore, achieving optimal performance requires careful attention to layout. following the suggestions below will improve the analog performance and logic noise immunity. 1. place the rext resistor as close as possible to the rext pin and gnd pin. this will minimize parasitic inductance and capacitance. 2. use a separate line to the device gnd pin for rext, and sepa- rate lines for the decoupling capacitors. the lines should join at ground. this star grounding will improve output load regulation and minimize any chance of oscillation. the rext ground line should carry only the small current from the internal voltage reference at rext. the high ac currents flowing through the decoupling capacitors and their resistive and inductive pcb lines cause noise (ground bounce) on the capacitor ground lines. such noise could disturb the reference voltage at rext and promote oscillation. connect the exposed thermal pad of the es and lp packages to the power ground, along with the decoupling capacitors, and not to the ground line for rext. 3. keep the output drive lines (out0 through out15) away from the rext pin to avoid coupling of the output signal into the reference for the current sources. output lines should not run adjacent to the rext pin or directly under the rext pin. 4. use decoupling capacitors on the vdd pin and the led sup- ply bus. place the logic decoupling capacitor (0.1 f, one for each a6282) as close as possible to the vdd pin. use at least one 10 f capacitor from the led supply line to device ground for at least every two a6282s. 5. use multilayer boards if possible. package power dissipation the maximum allowable package power dissipation based on package type is determined by: p d(max) = (150 ? t a ) / r ? ja , where r ? ja is the thermal resistance of the package, determined experimentally. power dissipation levels based on the package are shown in the thermal characteristics table. the actual package power dissipation is determined by: p d(act) = dc (v ds i o 16) + (v dd i dd ) , where dc is the duty cycle. the value 16 is the maximum number of available device outputs, representing the worst-case scenario (displaying all 16 leds). when the load supply voltage, v led , is greater than 3 to 5 v, and p d(act) > p d(max) , an external voltage reducer (v drop ) must be used (figure at left). reducing dc will also reduce power dissipation. the es and lp packages contain an exposed thermal pad on the bottom of the package for enhanced heat dissipation. connect this pad to a large power ground plane using thermal vias. jedec documents jesd51-3 and jesd51-5 give suggestions for pcb and thermal via designs. v ds v f v drop v led v ds v f v drop v led v ds v f v drop v led application information typical application voltage drops
16-channel constant-current led driver a6282 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package es, 4 mm x 4 mm, 24-pin qfn with exposed thermal pad 0.90 c seating plane c 0.08 25x 24 24 2 1 1 2 24 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only (reference jedec mo-220wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-25w6m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.00 0.15 4.00 0.15 4.10 0.30 0.50 4.10 0.50 0.75 0.05 2.10 2.10 2.10 2.10 0.25 +0.05 ?0.07 0.40 +0.15 ?0.10 b pcb layout reference view
16-channel constant-current led driver a6282 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 24-pin tssop with exposed thermal pad 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.00 4.32 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06
16-channel constant-current led driver a6282 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2008-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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